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Re: flyback design issue
Thanks for the reply. I will take a look at the PID control as you suggest. But in case the loop is open for DC I still get it to lock. That is what has driven my curiosity.
Hello,
I have this flyback smps circuit:
when simulating the behaviour I get the following output:
My question is if the behaviour of the error voltage (at the "+" input of U1) is correct?
The error amp has an open loop for DC in this configuration, is it ok?
Thank you for your answers.
BR.
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