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Thank you very much for your participation. It already helped a lot. But unfortunately, the main question still remains. Let me clarify my point:
Is it true that the main procedure goes in two steps: (1) load|unload data (2) capture the response from the combinational circuit?
Is that...
I've collected all the data, that I have. Netlist, schematic, scripts, patterns and Verilog testbench. We use a simple handmade library with basic 2-input gates and DFF/SDFF without any set|reset nodes. I will be glad for any tips and thoughts. Thank you for your assistance...
Thank you for your reply! I'll try to clarify some issues.
It is the simplest possible circuit - s27. It has 1 combinational block - only 9 logic cells; 1 scan chain with 3 simplest scan flip-flops without any set|reset. Only D, Q, NQ, CLK, SI, SE. Scan chain was generated by Synopsys DFT...
Hello. I have problems in understanding patterns, generated by TetraMax ATPG. I have simple circuits (from ISCAS benchmark) with full-scan DFT. And when I dive into patterns (.wgl or .stil) I see some strange things. 90% is predictable and clear to me:
scan_select is set to "1" (we are in...
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