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Recent content by tecsiun

  1. T

    CMOS latched comparator design

    preamp + regenerative sense amplifer
  2. T

    Looking for documents about comparators

    comparator the offset is important at the beginning of the comparison period. Due to the structure of a latched compartor (positive FeedBack), a small difference in its input should give an almost rail-to-rail output.
  3. T

    how to design zero crossing comparator with single supply?

    the offset is important at the beginning of the comparison period. Due to the structure of a latched compartor (positive FeedBack), a small difference in its input should give an almost rail-to-rail output.
  4. T

    Analog design in 90nm process

    It is normal that the gate of MOS has current because of the leakage current from gate to substrate for low-k . Added after 6 minutes: It is the challenge for the 90nm age.
  5. T

    who can solve this amp problem

    In many cases, feedback is used to solve stability problem, and it can be used to modify the input and output impedence.
  6. T

    question on comparator

    it can be used to modify the input and output impedence.
  7. T

    How to switch between two power sources?

    try a comparator which has a 3 V logic out and the analog part runs on 5V or so.
  8. T

    Simulation with dynamic comparator problem

    Design techniques for high-speed, high-resolution comparators
  9. T

    Oscillator Simulation

    add ".opt accurate" to the hspice netlist when do the simulation
  10. T

    How to simulater Oscillator

    I think you can decrease the timestep of simulation,and initial condition is added to the crytal oscillator 'ic=xmA' If you want speed up the simulation.
  11. T

    Crystal oscillator: How to simulate the equivalent negative

    when do an open-loop simulation, oscillator model should be included, ? If only use the inverter without oscillator model, we can get the gain of the inverter not open-loop gain. ?
  12. T

    mos in sub-threshold region

    and i am care of this title , thanks to nxing!
  13. T

    How to have HSPICE ignore open drain/source MOSFETs?

    All those open drain/soure MOSFET are usefull, if not, how can not set them NG?
  14. T

    [help]how to construct a circuit to test the phase margin

    can you use the tool--Hspice? in the AC set: AC=1 ,then .ac vp(OUT)

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