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Thanks for the reply's! I am a newby to verilog and am trying to get familiar with the syntax and structure. I thought use of the "case" statement required that the "cases" be sequential .. as in 1,2,3,4. Every example I have seen was like that .. obviously not. I will recode .. and look for...
I am using an if statement with multiple conditionals. Is there a shortcut way to write this as the "year_rt" is the same in each case .. but the condition is different. This is used in a string of "if" statements that doesn't lend itself well to using the "case" statement.
if ((year_rt ==...
ads-ee Thank you! I have changed all the code to non_blocking. The tenth counter is a 4 bit counter initialized to 0.
All this code is executes every .1 sec.
first_counter = 0;
tenth_counter = 0;
first_toggle = 0;
.....and is tested for a "nine" count before the time code and...
Thank you for the reply! I just noticed that I got a Synthesis warning message ..
This refers to the line marked with <<< below. Maybe this has something to do with my problem? This is how the reg is identified.
code snip...
reg [24:0] first_counter; // .1 sec counter for rapid...
Hello. I am new to verilog and to this forum, and have been trying to get an alarm clock working on the BASYS 3 FPGA board using Vivado 2019. All the code is working correctly except for the part that advances the time. The problem is that both the seconds and minutes advance together .. so...
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