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Recent content by tchisholmuk

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    DFT - Scan Data Output inverted (Design Compiler)

    Hi, I am using Design Compiler to insert a scan chain in a design, but when simulating after insertion the Scan Data Out is inverted with respect to Scan Data In. I can see the scan data being inverted at several points throughout the scan path, however it always ends up being inverted for the...
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    [SOLVED] DFT DRC - Clock connected to primary output (Design Compiler C17)

    "ScanMode" is not a valid type for set_dft_signal in Design Compiler (at least the one I'm using). I've tried to gate the clock with a mux and the Test signal (with type ScanEnable) : set_dft_signal -view spec -type ScanEnable -hookup_pin PAD_Test/C -port Test -active_state 1...
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    [SOLVED] DFT DRC - Clock connected to primary output (Design Compiler C17)

    Yes Not sure what you mean by this, I've tried using an AND gate to prevent the SLCK signal reaching the output port while scan is active, but this still results in a combinational path to the output. Wouldn't using a scan mux in the path have the same effect? Sure, the dft commands I've...
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    [SOLVED] DFT DRC - Clock connected to primary output (Design Compiler C17)

    Hi, I'm using Synopsys Design Compiler for a design which drives an LCD display, where the LCD's clock in (SCLK) is an output from the design. I'd like to clock the LCD at full speed and therefore use the system clock as the SCLK, effectively passing the system clock in to the design and...
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