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Is anyone able to please tell my why the capacitance vs frequency response of MOScaps degrades with increasing channel length?
Any help would be immensely appreciated.
I have an analog signal that is generated on-chip and is periodically reset to a known a known value (1V) resulting in a somewhat digital signal. In other words, the output signal goes from 1V to a low value (not zero) and then is reset to 1V and then drops to a different low value, reset to 1V...
I'm told that cadence is not recommended for high frequency simulations. I used cadence to determine the CV curves for a MOS cap and compared to measured data (from s-parameters) and there is a big discrepancy. Does anyone know if cadence's models are not accurate at high frequency and why?
Thanks.
Hi Goldsmith,
I both simulated using spectre in cadence and measured on-chip (the measured results are very different from simulated). The capacitors are MOS capacitors. In both cases the impedance decreases in the frequency range of interest and does not rise, which I assumed to mean that the...
When I simulate the capacitance of a varactor (nmos in an nwell) using spectre in cadence, the capacitance increases slightly with frequency. Other devices (standard NMOS and PMOS, MIM), the capacitance decreases with frequency which is expected. Is anyone able to please explain why the slight...
If the plot the impedance phase of a (non-ideal) capacitor is plotted and seen to approach -90 degrees, is it acceptable to infer that the ESL is negligible?
Thank you AmrZohny for the information. Is the minimum value still always used for digital blocks in multi-core processors running at relatively slow frequencies?
Just wondering how rise time scales with technology now that the frequencies are held approximately constant with the move to multi-core? Intuitively the transistors should still be faster since L is smaller so the rise time should get smaller. However, if the clock frequency doesn't change and...
How should S-parameters be measured correctly for MOScaps on a VNA?
Since it's an nMOScap I need to bias the gate at 1V to create the channel in the device. When I did this the capacitance values still look like those measure with no bias.
I use a DC power supply and a T to connect the DC...
I have two-port S-paramters from a VNA for some decoupling capacitors. I also have data from de-emdedding structures (open, short, through). How do I de-embed the pads/traces from the DUT data? I have no experience with RF, ADS, Sonet, etc. so the most user-friendly solution would be very much...
Where can I find accurate historical scaling data for the supply voltage of CMOS technologies since the 70's? I assumed this would be easy to find on-line but am not having much success.
Hello,
Just wondering if data-gating is often used in static logic ALUs and what the advantages/disadvantages are? For example, in an ALU comprising an adder and a logic block (AND/OR/XOR), is the data to the logic block or adder gated and activated only when needed during specific cylcles or do...
Hello,
Just wondering if data-gating is often used in static logic ALUs and what the advantages/disadvantages are? For example, in an ALU comprising an adder and a logic block (AND/OR/XOR), is the data to the logic block or adder gated and activated only when needed during specific cylcles or do...
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