Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Please for FinFET models (pfet and nfet) , I watched from the comments that their nodes are declared in this order:
D S G1 G2 B
but in PTM-MG FinFET models , nodes are declared in this order:
mnfet d g s x nfet
how can i decared the backgate (double gate)??
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.