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Recent content by taranom1

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    Is this a jitter in output signals!?

    If you mean PTL logic, no it is based on a hybrid logic. Here is test bed of 16 bit adder I used.
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    Is this a jitter in output signals!?

    Hi! In transistor level, I simulated a 1-bit full adder cell and the transient response of output signals were ok, Until I tested it in a 16 cells successive full adder, a unstable state occured in outputs in specific transitions of inputs periodically (picture attached).This state has increased...
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    Wn/Wp in digital circuit

    I mean that for wn/wp, 60/120 is same as 180/360?
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    Wn/Wp in digital circuit

    Hi all! How can I determine Wn/Wp ratio exactly by having Vth in digital circuit? In full swing digital circuits the input and output are equal to vdd or 0, so are the Vgs and Vds equal to vdd or 0 in equation below? Do I have to use triode and saturation equations for each transistor...
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    32nm CMOS technology file

    I have used the asu library, but I don`t know whitch of the models in http://ptm.asu.edu should I use. I used bulk-cmos model generated by online tool in nano-Cmos part of asu website. But I don`t know how to get technology specifications like Leff, Tox and Rdsw.
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    32nm CMOS technology file

    Hi all! I need 32nm technology file to simulate a full adder using hspice. I found ptm technology file for nmos and pmos, but the full adder didnot have a correct output pulse. I would be very grateful if everyone ‎could guide me.
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    [SOLVED] Test-bed Propagation Delay

    Thanks all of you!
  8. T

    [SOLVED] Test-bed Propagation Delay

    Thanks for the answer, Should I remove buffers and Cloads of test-bed in circuit alone mode or they will remain and I should measure from after input buffers to before output buffer? I want know the usual way article writers use.
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    [SOLVED] Test-bed Propagation Delay

    Hi all, Is the propagation Delay measured for the whole test bed or for the circuit alone ,usually? I mean that Should I remove buffers and Cloads of test-bed for measuring delay in circuit alone (circuit under test)mode? Detailed Image have been attached.
  10. T

    Choose an appropriate transient simulation length to measure power consumption

    Thans dick_freebird! I think the reason I can`t achieve to article values exactly is that maybe it`s test-bed or trise/tfall are different. Now my question is :If I change Frequency(by changing test patterns pulse width),I should change Power Consumption measuring length too?(because pulses end...
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    Choose an appropriate transient simulation length to measure power consumption

    How to Choose an appropriate transient simulation length to measure power consumption of VLSI circuits with Hspice? also what value can I assume for trise and tfall in my PWL source?(because trise and tfall effect to delay and Power values.) Power Consumption and Delay values arenot equal to...
  12. T

    MAX delay in HSPICE

    Can I use absolute value for Rise and Fall times?
  13. T

    MAX delay in HSPICE

    Thank you dick_freebird! I tried to earn delay of all inpus to outputs from cosmosScope/wave viewer delay func and max of them is very near to the result in .lis file (in spite of negative values),just with 0.2 pico difference. Could you plz Write an example about clip func, I Couldnot find...
  14. T

    MAX delay in HSPICE

    Hi again, I examined several times but I didn't know how can I set trigger befor target:-|. Is it related to Delay or rise and fall time of input pulses? this is part of my input pulses and measure delay: VA A Gnd PULSE (0 vdd 2ns 100ps 100ps 5ns 10ns) . . . .measure tran delay_ar_C TRIG...
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    MAX delay in HSPICE

    Could you please explain more.I don't have electronic base! in another code I use fall=1 ... rise =1 insead of cross , but it cause negetive results too. I have another question too: in test bed of full adder we should get pulse after first output buffer or before that?
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