Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by taoly

  1. T

    How to realize a non-integer delay in simulink?

    就没有人知道这个问题吗?
  2. T

    How to realize a non-integer delay in simulink?

    I want to delay a signal by 1/2 sample period in matlab, but the delay function block in simulink is all for integer delay. Does anybody know how to realize the 1/2 delay? Thanks!
  3. T

    Hspice .measure question

    I run a amplifier AC simulation with hspice. I wonder how can i get the output gain at different input signal frequency(such as 1kHz) by .measure? thx.
  4. T

    ESD Protection Question

    In many COMS circuits, the ESD protection circuits are offen constructed with large NMOS or PMOS. I want to know what is the relationship between the ESD robustness and the sizes of these MOS transistors. Is there any papers or documents about this question? Or any simulation method? Thanks!
  5. T

    utilities of Astro----scheme2pdef

    Does anyone know where to download this utility on synopsys ftp site. thanks a lot.
  6. T

    utilities of Astro----scheme2pdef

    Does anyone know where to download this utility on synopsys ftp site. thanks a lot.
  7. T

    How to convert spice gate level nelist to verilog netlist?

    spice to verilog Does anybody know how to convert spice gate level nelist to verilog netlist? Please help me . thanks a lot.
  8. T

    Cadence Schematic and Layout File

    I have tried the above two ways, but it's in vain. Who can help me?
  9. T

    Cadence Schematic and Layout File

    I have a partial directory of what used to be a part of cadence library designed on an old version of cadence (probably in 1990). A lot of files are missing, cds.lib is also missing. The directories I have are named after the respective subcircuits they belong to. Each directory has subfolders...
  10. T

    single/dual/multi-port SRAM

    Does anybody know what's the defference between single-port SRAM and dual-port SRAM, as well as multi-port SRAM? Is there any documents for SRAM design? thanks a lot.
  11. T

    Looking for documents on Clock Tree Design theory

    books on clock tree synthesis I am a newer in digital circuits design. can anybody provide some documents or link for Clock Tree Disign theory?Thanks a lot.
  12. T

    How to calculate the input capacitance of I/O cell in Hspice

    input capacitance in hspice or spectra, does anyone know hot to get or calculate the input capacitance value(Cin) of a I/O cell? help me. thx!
  13. T

    Does anybody have technology documents about I/O design?

    I/O circuits design Does anybody have technology documents about I/O design, such as TTL, CMOS, SCHMITT I/O cicuits design? Could you share or supply a link? Thanks a lot!
  14. T

    The difference between dBm, dBm0, dBmP units

    I am confused with these units. Who can help me to understand the meaming of them, or suggest some related documents. thanks a lot.

Part and Inventory Search

Top