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I have a problem synthesizing my design.
Its submodules can be synthesized however when I want to synthesize the top module, Genus doesn't finish the elaboration.
But there are no errors, because I check it with Modelsim to see if there is any. Also by reading the HDL file in Genus I don't...
Hi,
I need to implement an hdl of hyperbolic tangent for Artificial Neural Network activation function.
I've searched a lot but unfortunately I wasn't able to find a proper version as most people have used IPcores to implement it.
Could anyone help me with it?
Hi,
I need to generate a saif file for iscas 89 s38417 benchmark. I need a good testbench for that.
I searched the previous posts and I found a link for that but it doesn't work anymore. could anyone help me with that.
Do anyone know how can I extract MOSRA Level 3 parameters for a specific library file when I'm using hspice? I wanna measure the aging for standard cells of that library.
Also do these parameters will change based on temperature?
I've found a video about that in synopsys website but it doesn't...
Hello,
I'm trying to send and receive data to/from fpga using ft232rl module(rs232). I'm using mojo v3(spartan 6 lx9). however I have tried to produce baud rate and receiver module, I'm not able to receive data from ft232rl.
my baud generator is like this:
module baud( clk, rxclk_en );
input...
yes I know but I will use the combine of this bits in my code!
for this reason I want to know is there any solution to reduce this long transition?it's so important for me.
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Actually I have another question.
If I try a code like this at asic does it have a long transiton...
could you please explain more about DMEMs/registers?
I defined data_out as an output port and I didn't specify that it's a reg or wire.I think in this case verilog HDL consider it as a wire by default,isn't it?
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Actually I've used rising edge.
and I exactly wnat to know...
I did the xst synthesize and the maximum frequency was about 350 MHz.
but when I do post place and route simulation there is some problem with my results.
this is my code:
module
ram_top(
clk,
en,
we,
addr,
oen,
data_in,
data_out
);
input clk, en, we, oen;
input [5:0] addr;
input...
actually I think I do it correctly because when I change the prefered language to vhdl and then use core generator it works.
but I don't know the exact reason unfortunately.
I hope someone could help me.
I checked https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgn_c_df_synthesize_verilog_design.htm
but it was no special instructions for xilinx ISE to solve this problem.
Can you explain it more(adding a syn_blackbox synthesis attribute to the module)?I don't have any idea about it.
hello.
I try to implement a distributed RAM using ISE IP core generator but I have this warning:
WARNING:HDLCompiler:1499 - "E:\M.Sc\ISE projects\ipcore-test\test2\ipcore_dir\myram.v" Line 39: Empty module <myram> remains a black box.
my verilog code is :
module test2(
data_in,
clock...
oh that was a mistake of copy paste.thats not the problem if you correct them and then run post simulate you can observe the problem. I changed the length to generate xst reports but I forgot to change testbench.
it was just a copy paste mitake.
and the code is from xilinx pdf...
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