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Recent content by talpina

  1. T

    Need VCXO PLL Design for T1/E1 (ref. des, methods, etc.)

    if you need only to extract clock and timing you can use or LIU(line interface unit) and Framer (you can also implement it in a FPGA) or you can use a single chip (liu + framer ) that perform all operations. the only one that you need is a oscillator +- 50 ppm to meet the E1 requirements. look...
  2. T

    Need VCXO PLL Design for T1/E1 (ref. des, methods, etc.)

    TO RESPECT THE G703 REQUIREMENTS YOU CAN USE A SIMPLE 2048 +- 50 PPM OSCILLATOR THAT NOT REQUIRE A HARD SCHEMATIC
  3. T

    XILINX ISE 5.1 INSTALLATION PROBLEM WITH WIN2000

    xilinx 5.1 installed ise5.1 on win2000 italian and english but never this problem. do you use any service pack?
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