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So the Path Delay Fault Model is tested using a robust or nonrobust path delay test. I am trying to differentiate between the two and am having trouble.
What are advantages/disadvantages of each? When is one method preferred over the other?
Thanks,
talon
I am having trouble understanding gain in the single ended OTA case and its use in creating an op amp.
Say I have a first stage that is an OTA - diff pair with current source load. This diff pair has transistor M1 on the left and M2 on the right.
In small signal I input Vin at the left input...
I understand your math but can you explain why (3.35) shows Av = |Vgs2 - Vth2| / |Vgs1 - Vth1| while Av ~ |Vgs1 - Vth1| / |Vgs2 - Vth2| from (3.36) and (3.37). This is like saying A=1/A.
So I have a question about this topology. In Razavi's text Design of Analog CMOS ICs he proves that gain is proportional to the ratio of the overdrive voltage of the pmos to the nmos.
Av = |Vgs2 - Vth2| / |Vgs1 - Vth1|
But then he says gain is ~ gm1/gm2 which means gain is inversely...
Thanks for the clarification. I agree that layout is tough, mostly because the errors I read off in DRC don't make much sense to me. Guess that will get easier with experience. Any good books on how to become a layout master out there?
So, I'm just going through my first college course on analog IC design and was wondering if there are any resources out there that will really teach me layout techniques well (Cadence Virtuoso)?
Also I see a lot of free online tools for PCB layout and am kinda confused where it fits into the...
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