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The leading contributor to the spike looking more negative than it really is would be probing inductance. If you use good probing techniques to to reduce the parasitic inductance, you should be able to get a good accurate reading.
You can use a diff probe with pretty good common mode rejection...
The switching loop is relative to PGND so you can still see a negative transient on GNDA relative to PGND/GNDB. You're right it won't be relative to the logic GND. Does it matter if GNDA shoots very negative relative to GNDB? Maybe - perhaps the datasheet has more details on it and I missed that...
Don't forget to consider the negative max voltage rating for the pin that connects to the high-side FET's source. What you need that to be will depend on your application and layout. The 2ED2106 datasheet clearly specifies -11V rating, and section 5.9 calls this out.
From purely a power density point of view, also look at the Pilawa group's work at 216W/in3.
https://pilawa.ece.illinois.edu/little-box-challenge/
1699180400
In essence, it comes down to reducing the volume by targeting 2 aspects:
Typically your passives (especially magnetics) occupy the...
**broken link removed**
Rp is the parallel resistance/impedance of your input current source, Rin in the input resistance/impedance of your circuit, which I've represented as an amplifier as U1 here.
If Rin is low (relative to Rp), most of the current I flows through Rin and thus through the...
My guess would be that it uses an SG3525 (or similar PWM chip) and drives 2 MOSFETs in push-pull configuration. So the transformer would be center-tapped on the low voltage side. The high voltage side has the voltages marked on the board. Hard to tell if it has feedback or not without seeing if...
Because of Id, Vout sits at some large-signal DC bias voltage, which is then used to bias the gate of the NFET. This is necessary since the AC coupling at the gate of the NFET will remove DC components and the NFET wouldn't be working properly unless biased at some reasonable VGS (and VDS).
The...
One possibility:
For the first stage, consider using a folded cascode topology (with PMOS inputs) to get high gain with good voltage headroom. For the second stage, use a topology for low output impedance and good swing - eg a common-source stage with active load.
You may want to consult a good...
As erikl mentioned, instead of halving the width, you can double the length, for example. Keep in mind that as you change the length, you change ro (=1/gds) which changes roughly proportionally with the length.
IoT relies heavily on sensors, which are analog in nature. Hence, any sort of analog signal conditioning circuit, integration of different sensors, etc before data is quantized seems like a natural choice.
Adding on to what Calika mentioned:
1) If VDS > Vth, you get the square-law relationship between IDS and VDS (since VGS=VDS). If VDS < Vth, you get subthreshold conduction -> you can think of the FET as being open. Thus, you have current in one direction and not the other - thus a diode...
Solve for Vout in terms of Vin by doing KCL at drain. That'll give you your required ratio.
In your SSM, you have Ig going through Rs - Ig is current into gate, not into Rs.
If operating as a switch, you go from saturation to cutoff (or other way round) as you mentioned. As Vbe increases, for a short amount of time, the transistor will be in active (linear) mode until you enter saturation. But you want to design such that it spends as little time as possible in the...
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