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I have downloaded TCL source from here and I can compile it to generate static library in Windows7 using the following command
nmake -f makefile.vc OPTS=static INSTALLDIR=path_to_your_install_dir
nmake -f makefile.vc install OPTS=static INSTALLDIR=path_to_your_install_dir
In the output, I can...
hello,
I meant by Question 2 is: P is M appended by the CRC. If you reviewed the link http://www.sunshine2k.de/articles/coding/crc/understanding_crc.html
it mentions in section 8.2 that "The CRC value is appended to the input data which corresponds in school arithemtic to subtraction." That is...
Hello,
Can any explain please how to understand CRC-32 algorithm for Ethernet. I understand the following:
1- There is an ethernet message M
2- There is a polynomial G (in case of Ethernet it is 0x04C11DB7).
3- M is multiplied first by x^32 (I don't understand why?)
4- CRC value is ...
In my testbench readReq is synchronized. please find below my testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fifo_tb is
generic(
RAMsize: integer := 256;
DataWidth: integer := 8
);
end fifo_tb;
architecture tb of...
Hallo,
I have simulated the following code using ModelSim.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fifo_SCnt is
generic(
RAMsize: integer := 256;
DataWidth: integer := 8
);
port(
clk: in std_logic;
rst: in...
Hello,
I had a component in my VHDL design. some ports of this component are not needed to be connected. I have used 'open' in port map section. This works ok for ports of mode out. for ports of mode in, I have to set initial value for the port first. As an example
Component HalfAdder
Port (...
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