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Hi,
i am interfacing virtex 5 with ddr2.
I have generated a code for ddr2 using MIG. i am getting the following warning.
WARNING:Timing:3223 - Timing constraint TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY
FROM TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO TIMEGRP "RAMS" TS_SYS_clk0 *
4; ignored...
Hi,
i am interfacing virtex 5 with ddr2.
I have generated a code for ddr2 using MIG. when i run this MIG ddr2 code as an individual toplevel module it runs smoothly and works fine. however when i use this code as a submodule in another toplevel file i get the following error during mapping...
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