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To improve test-ability during scan we are thinking of splitting the functional reset in to 2 resets, being dft reset and system reset, during scan test mode.
Which means, while in scan test mode the tap controller can not be reset and the system reset will follow the reset input pin without...
Thanks for the comment.
We have our own custom HAPS ;)
We created a specific carrier board which can hold an COTS FPGA, which will be used as stimuli block, and a custom add-on board with socket, which will contain a device under test.
For the last we would like to have a drop in replacement...
I need a large FPGA with as mush as possible LE/CLB only (or near to).
The reason is that I need to emulate our ASIC design on it.
The design does not make use of any particular interface like SerDes, PCIE etc etc.
Any one an idea which device to select ?
br,
Simon
Personally, I think it is.
It gives tons of learning experience.
Theory can be quite different than real world.
Next, investigate in getting a "free" vendor-locked (modelsim) or open source simulator like ghdl/icarus with GTKwave and invest time in getting proper test-benches and regression suites.
I guess not much.
It also depends on the logic implemented in the FPGA.
Vivado has understanding of the device it is compiling the code for. So it probably has taken the best optimization already.
And remember; synthesis tools are better at optimizing than you are. People at e.q. Synopsys are...
It is quite easy to obtain one. Just have a google.
Ebay offers used board. And probably both Aliexpress and Ebay offer chinese manufactured cheap and simple boards.
More expensive one come from Terasic or Digilent etc
Simon
Not with JTAG.
Xilinx has app-notes on how to program their FPGA's via the "normal" programming interface.
See :
https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
Many years ago some one told me that it is better to have a verilog/SV testbench for GLS rather than VHDL.
Can some one please explain me why ?
best regards
Simon
I am writing a makefile to do a regression suite.
It is using the 3 step approach in Cadence (compile (ncvhdl) , elaborate (ncelab), simulate(ncsim))
The makefile includes a testcases.mk which looks like :
testcase_list = \
testcase1 \
testcase2 \
I want to use this list in my Makefile...
To my humble opinion 2 process state machine are as good as 1 process.
The outputs of the 2 process style are directly related (and so probably taken as well) from the state registers.
grtz
ST
Hello,
Have you got any idea what your architecture of the thing you will build shall look like ?
From there you can decide what to put in FPGA or SW and what the requirements for your FPGA should be
(eq no. of pins , adders, multipliers, block RAM and etc)
Take some time to draw a picture of...
Two options :
- write a boot loader
- have a uart, like what geisler did, with an address bus and data bus to get access to the ram containing the program code
sythe
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