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Recent content by systemfly

  1. S

    this VIOLATION?????????

    sorry! The clock period is 14 Added after 4 minutes: I known! thank all!
  2. S

    this VIOLATION?????????

    the timing script: set_driving_cell -cell pp3t01 -pin PAD -library cb35io132_max [all_inputs] set_load [load_of cb35io132_max/pp3t01/OEN] [all_outputs] set_max_transition 2 [current_design] set_max_area 0 set CLK_PRD 10 create_clock -name clk -period $CLK_PRD [get_ports clk]...
  3. S

    this VIOLATION?????????

    It is nano seconds, "U282/ZN (oai221d2) 158.42 158.42 f" I dont known how this delay generate I thought the path delay is smaller than 10ns
  4. S

    this VIOLATION?????????

    library setup time transition Startpoint: rst_n (input port) Endpoint: v_data_array_reg[0] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------...
  5. S

    how can I run this example

    Could you select the device?
  6. S

    Looking for UART code using FIFO in Verilog

    UART code needed **broken link removed**
  7. S

    Where to get a free Xilinx ISE software?

    Xilinx ISe www.xinlinx.com
  8. S

    Documents for learning SystemC

    systemc books download I think SystemVerilog is better
  9. S

    Who has dc-tcl scriprt?

    dc tcl hi,all Who has dc-tcl scriprt? Please send to wang_nan_fei@yahoo.com.cn Thanks!!!
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