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For VHDL, if you combined it with a verification methodology, such as OSVVM (current VHDL market leader) and ran it on GHDL, that would be interesting. OSVVM is at https://github.com/OSVVM/OsvvmLibraries.
You are not too clear about your capability. Can you create tests that exercise all...
If your device is an ASIC or a fuse based FPGA, your device can power up in any random state, and then reset is applied taking the statemachine to idle. How do you assure that reset actually works? What if reset to one of your statemachines was connected incorrectly?
If your device is...
You would want to look at the part/board to see if the FIFO is for data or DMAC setup.
WRT data, the DMAC is reading from one interface and writing to the other. If the writing interface stalls, the read can complete a couple of operations before it stalls. They must be confident the...
Your DMA controller is moving data from one location to another. Locating it between the AHB and APB is going to allow it to address the AHB memory (on AHB) and move items to the SPI master (on APB).
Putting your DMA controller on AHB without anything co-located will require two accesses to...
When you are doing a fixed transfer, where is the data going to? Most likely it is an an IO device where you are writing into a transfer FIFO or holding register for the interface. To read these values, you would need to check that the receiving side of the interface received the correct...
Most of the terms we use have some degree of ambiguity.
BFM is Bus Functional Model. All this means is that you have represented something with fidelity at the interface level. For example, for a CPU, it would represent the READ and WRITE operations the CPU does at its interface (such as...
@dpaul
> VUnit also has plugin for OSVVM.
VUnit only includes the OSVVM utility library. I think the intent there is to facilitate using the OSVVM RandomPkg and CoveragePkg with VUnit.
OSVVM is more than just a Utility library (also called OSVVM), OSVVM also includes a Verification...
@dpaul OSVVM provides a complete solution - from basic stuff like Message Filtering (logs), Error Handling (alerts in OSVVM), and Self-Checking (affirmations) - to verification capabilities like Functional Coverage and Randomization - to verification data structures like Scoreboards, FIFOs...
OSVVM does not run yet under Xilinx tools. If you want to use it with Xilinx tools, file a bug report against their tools.
OSVVM does run under Aldec ActiveHDL/RivieraPRO, Siemens ModelSim/QuestaSim, GHDL, and Synopsys VCS. We are working with Cadence to get our entire regression suite working...
The message does not mean it "fixed" your timing loop by removing it. It means it is ignoring it because the presence of the timing loop causes the timing tool to be in an infinite loop.
It is actually quite simple. Make a short list of companies you want to work for. Find out what they use. Learn that.
What is the market really doing? Currently a basic SystemVerilog simulator costs much more than a VHDL simulator. EDA vendors have made a big push to get people to switch...
TrickyDicky,
1 & 2 already have proposals for VHDL-201X. Be sure to fill out a priority sheet and rank them high if you need them. I find it particularly painful without 1. It would allow me to do a registration layer for coverage modeling. It would also simplify my indexed scoreboard model...
During the VHDL-2008 language revision, I look into what it would take to add Functional Coverage as language syntax to VHDL. Unfortunately, if we did a "me too" implementation of what SystemVerilog, it would require OO constructs (which VHDL almost has in Protected Types). We, the working...
Re: Can VHDL be used for "functional coverage"? Why not?
The OSVVM community has grown beyond 1200 members.
OSVVM's functional coverage capability is quite good. WRT to cross coverage, it is likely some what more capable than SystemVerilog.
In addition to seeing OSVVM.org...
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