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Recent content by syncom

  1. S

    DC0509 setup problem!

    how about lmgrd -c {your_lic} and check status by lmstat -c {your_lic}
  2. S

    difference between SAIF and VCD file

    saif power estimation saif file and vcd both needed for power analysis nd optimization? if you have gate level vcd file , you don't need saif file and you can analysis your power . because prime power can get those switch actitive/ toggle rate /sp from vcd file.
  3. S

    how to delay bus for about 2 or 3ns compared to the clock

    how to delay the bus? May the re-synthesis and add set_input_delay -min 2ns to solve it ?
  4. S

    [SOLVED] Any Book to learnTetraMax..

    Attached one more.
  5. S

    [SOLVED] Any Book to learnTetraMax..

    How about the Teramax User Guide ?
  6. S

    howto determine the FIFO Depth

    FIFO Depth Output is 1 bit serial data at 50 MHz, I need to maintain my throughput at 500Mbps? May you explain it more detail ?
  7. S

    Wat does (!==) Verilog operator mean?

    verilog question suggest to use casex , it is synthesisable..
  8. S

    three quetions about prime power

    primepower start command below is my script,give you some ideal: set search_path " . /home/lib/libadm/faralib/0.13um/fsc0h_l/current/GENERIC_CORE_MINILIB/FrontEnd/synopsys" set link_library " * fsc0h_l_generic_core_minilib_wc.db dw_foundation.sldb " read_verilog top_gate.v -hdl_compiler
  9. S

    synchronous frequency divider design.

    which reference book i can refer?
  10. S

    VHDL/Verilog Editor under Linux

    verilog under linux I always use Vi ,because it is strong enough to edit verilog/VHDL .
  11. S

    Adobe Acrobat Professional in Linux ?

    DO it really have Perofessional in Linux ??? I only see Reader for linux !!
  12. S

    [Help] run DC under Linux

    to all: I install synopsys DC under Redhat 8.0,But when I try to execute "read file/analyzer file" commond in the GUI ,DC will be closed and jump back to shell.Then It will show a Error message ,anybody help me please!!! below is the Error message ... ..... Initializing... Error id=489925...
  13. S

    [Help] Could NCverilog run many testbench in sequence?

    Thank you ,Nobody! But I still have question in $test$plusargs and -R argument,because if I need to run 10 files in sequence (I mean the second testbench will start to simulate after the first testbench complete over,and the third one will start to simulate after the second done,and...
  14. S

    [Help] Could NCverilog run many testbench in sequence?

    To all: I had a problem in NCverilog ,because I had 10 testbench file to simulate my target file.I want to write a script file to Run the 10 testbench file in sequence, But I don't know how to do ? Ps: I had wrote each script of 10 testbench file,But I can let NCverilog run those 10 script...
  15. S

    [Help] Could NCverilog run many testbench in sequence?

    always @(*) ncverilog To all: I had a problem in NCverilog ,because I had 10 testbench file to simulate my target file.I want to write a script file to Run the 10 testbench file in sequence, But I don't know how to do ? Ps: I had wrote each script of 10 testbench file,But I can let...
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