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Was dr...
I have over one year experience of working in verilog and FPGA Kits (Both Quartus and ISE) and have done several projects including one major project of designing OFDM PHY...
I can teach you through the initial stage of entering into the design work. I also have extensive computer...
Re: 1.5/3/6 MHz Clocks from 50 Mhz On-board Clock using PLL
Thanks for ur reply
But .exe is not opening .... THE APPLICATION FAILED TO INITIALIZE PROPERLY is the message ...
Can u help me in that ?
Hello friends
In my project 'FPGA Implementation of OFDM PHY - 802.11a Complaint', I hav to support 3 mandatory data rates of 6/12/24 Mbps.
The Frequency on which the PHY-MAC interfacing module (PLCP) is running is computed to be 1.5/3/6 MHz for 6/12/24 Mbps respectively. The rest of my...
vlog-1902
Hello all ...
I am using Altera's FFT V 7.2 (FFT Megacore Function) in my project 'PHY Layer Designing of 802.11a Transmitter'.
While trying to simulte the FFT Core in modelsim 5.7g (Through TCL Script) using the same approach as mentioned in the guide of 'FFT MegaCore', the...
Thanks for the prompt response ...
I will look into both of these possiblities ... but why we cannot represent floating point values by Double Precision Floating Point Representation (64_Bit), Single Precision Floating Point Representation (32_Bit) or Half Precision Floating Point...
Hello all ...
Im working on the project 'FPGA Designing of 802.11a Transmitter' for the past 4 months as my first HDL Project n im having a difficulty in deciding the format suitable for representing the floating point values of I n Q in the mapper module.
The mapper maps the bits as per the...
Hello all ...
Im working on the specified project for the past 4 months as my first HDL Project n im having a difficulty in deciding the format suitable for representing the floating point values of I n Q in the mapper module.
The mapper maps the bits as per the constellation table n the...
readmem verilog
Hi
thank for ur reply but my question is WHERE IS THAT "code.vec" file defined ? im using modelsim 5.7 for almost 2 days and hav used ISE simulator for almost a week and couldnt find the solution
where the INPUT FILE is kept and compiled ?
I hope u understand my question
Thanks
readmemb
hi all
im using the ISE simulator for modelling of the modules involved in my project and i want the data to be read/write from/on the files ...
my question is : in the format of the readmemb("file_name",memory name,..) where is that file_name located ... will that be on the desktop...
hello friends ..
im in initial stage of desiging h/w of 802.11a complaint PHY layer .. and need some reference book dedicated toward hardware designing of OFDM PHY .. or any paper / document would equally be useful ..
waiting for a reply ..
Regards
Syed Shaheer Javaid ..
Hello all ..
Im designing hardware of PHY layer of Wi-Fi (transmitter part only) and after going through the standard and related hardware I still hav some queries un-answered .
My first problem deals with the input and output ports of the PHY layer i.e. if i want to represent my whole...
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