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Recent content by swolf

  1. S

    PMOS switch bulk connection

    hi all I have a problem when I design a sampling circuit. The sampling cap is very big, so the switch (which is a CMOS switch) resistance should be very low to get a good sampling presicion. but the PMOS size is very big to get a low resistance. The bootstapped switch is not suitable...
  2. S

    Band - gap reference for ADC

    Re: Band-gap ref for ADC I have the same confusion as dipnirvana, It seems as if the calculation is not wrong. My present opion is: first, it seems impossible to design such a bandgap to us, even to the big companies such as ADI (deduced from their product datasheets). secondly, we often do...
  3. S

    Could this circuit be used?

    yeah, it's a positive feedback. it could be used as a part of the latch.
  4. S

    MIM capacitor mismatch

    capacitor mismatch units does MIM capacitance need to be matched with the matching techniques such as using the unit capacitance array?
  5. S

    how to choose bjt for bandgap reference

    bandgap reference requirement I agree with bastos
  6. S

    How to start a design with a new cmos process technology

    I am working with 0.18 proccess, and I found that the method a) is good. I calculated out the Kn, Kp with the parameters in the model file, which are precise enough for hand cal.
  7. S

    comparators with 1.8V power supply

    I am designing a dynamic comparator which is composed of a preamp and a latch, i.e. the attached figure. the input signal is differential and it is sampled and subtracts Vthreshold with a swithed capacitance circuit (omitted in the figure). the process i use is 0.18um, and the parameter...
  8. S

    the offset of the dynamic comparator

    offset, dynamic comparator I am designing a comparator which allows +- 50mV offset, is the architecture attached here easy to achieve the specification? the process is 0.18um, and the power supply is 1.8V. thank you in advance!
  9. S

    the proper value of Vgs-Vth of the input MOST

    i am sorry that i typed a wrong value: Vds should be 1.187 V gm=2*Id/(Vgs-Vth), when Id is fixed, we can obtain larger gm by decreasing vgs-vth, is that right? so what will happen to the circuit when input mosts operates in the sub threshold? thank you
  10. S

    the proper value of Vgs-Vth of the input MOST

    I am designing a folded cascode OTA for pipelined ADC. It requires 400M Hz GBW with lowest power consumption. the load capacitance is fixed (i.e. 4 pF), so i need to design the input MOST to get the largest gm under the lowest id of the input MOST. as we know, gm is inversely propotional to...
  11. S

    simulating the settling time of "FDA with SC-CMFB"

    sc settling thank you very much hr_rezaee, could you please tell me where is the sample and hold circuit? a vhdl model in cadence?
  12. S

    simulating the settling time of "FDA with SC-CMFB"

    ota settling time I have designed a Fully Differential Amplifier (FDA) with Switched Capacitance CMFB, which is used in pipelined ADC, but I wonder how to simulate the settling time of it. It is different from the OTA with continuous time CMFB because it's working in discrete time or just one...

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