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Re: Sigma-Delta Modulator in Fractional-N frequency synthesi
Hi, leo:
There is a trade off.
So a system level simulation is needed. u can evalue ur system and determine
these parameters on basis of ur sim results. I use matlab/simulink programs.
beside, u have to take pll bw in to ur...
some papers and book give the formula.
The book: CMoS pll synthesizers: Anaylysis and Design. by Sanchez.
I can't remember paper titles.
copeland's papers maybe. you can search them in IEEE.
It is.
But for different DC input, DSM has different performance. Many theories try to explain this.
That is why dither is so important in Delta sigma pll
and time domain modeling is necessary.
for a 1st order DSM, the best location to add dither is the node before the comparator(1 bit ADC)...
phase noise from dsm is actually the dsm quantizaion noise. The quantization noise can be transformed to the pll input noise and then we can get pll output noise from dsm.
current mode logic logic levels
the input signal is current mode logic level , from 1.2 ~0.8.
I need to use full swing logic level 1.2~0.
Speed is around 2GHz, 0.13u CMOS. And duty cycle is important.
Is there any robust Circuit ?
Thanks in advance.
hi,MSSN,thanks for reply.
I just want to know exactly the deviation of frequcy that cdr can capture with pd alone.
I have read razavi's book already.
It doesn't descript circuit implementation on
CDR lock in detector design, I think.
Woule u give more details? Thank u.
for CDRs employing linear or bangbang PD,
what is there capture range ?
will cdr lose lock if large jitter appear in input data?
then what kind of jitter is more harmful? DJ or random jitter?
Is there possible method to design a robust lock in detect circuits to judge cdr in
lock or not?
Thanks.
In this figure, Integrator is in integrate phase. Cs is sampling cap.
Cin is parasitic cap in the input of op, Cf is feedback cap,and Cload
is load cap at the output of integrator.
Ceq in open loop state is given : Ceq_open=Cload+(Cs+Cin)*Cf/(Cs+Cin+Cf)
and Ceq in closd loop state is given...
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