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Recent content by swapnashah

  1. S

    Instantiation problem

    hi all, how can i make a top module in verilog code? it means dat two modules are instatiated in top module and i am giving input to a first module and output of dat module should goes into the input of the second module. the final output should be from the second module. pls help me out...
  2. S

    [POLL] Program your FPGA?

    i use verilog for my project soi ll prefer verilog.
  3. S

    verilog code for processor instruction

    hi all; can anyone help me to write down the code of one processor instruction in verilog???? the instruction is LXI B,2050H. while this instruction executes it will load 16 bit data 2050H into the register pair BC. If anyone has any idea abt it pls send me....
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