Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
My friend had faced this question during an interview. The answer is as follows:
Critical path in the SRAM is activated when a logic 1 is read from the cell at the first row's last column. This constitutes the critical path because when the word line is asserted from the row decoder, it has to...
HI
In memory TSB means Transparent Source Biasing :razz:
It provides an opportunity to suppress the leakage of SRAM Cell without going in the light-sleep, deep sleep or shut-down modes.
Please correct me if i am wrong :cry:.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
