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Hey all,
I am using Verdi for simulation of RTL. We have lot of assertions in design and I would like to know if an assertion is fired in a simulation or not. There is a assertion debug mode which should list out all the assertions, however, I am not seeing any information if it is passing...
Let me try to simplify things. Output going X is just a simulation thing. In Silicon, the output always settles to a definite value after having intermediate values between 0 and 1. With synchronizers, FIFO or other mechanisms to reduce metastability you can not guarantee correct output but you...
I am writing a test bench where I am randomizing few inputs using $urandom_range(max,min). However, every time I am running my test, it is returning same value. I would like to understand why I am getting this issue.
Thanks!
I will suggest you to take a look at D flip flop internal structure and see how asyn reset factors into output. Coming back to your question, if switching delay of reset from 0 -> 1 is extremely slow in that case actual circuit will not reset until reset is logically 1. Also from simulator...
Hey,
I just switched to Cadence SimVision from Verdi for simulations. For parameterized multibit signals in waveform dumps, I am seeing hex values instead of parameter names. I looked into preferences but could not figure out. I will appreciate if someone can help me here.
Thanks.
Re: Static Timing Analysis
Generally if you have a setup violation on a given path, you do not have hold violation on same path. You can probably have hold violation on some other fanin cone of endpoint which you can fix by adding buffers. Using lvt and hvt cells is a common practice. I am not...
Of course you cannot add synchronizer for multi bit data and this is due to reason #1 (no guarantee for delay). You will need DMUX synchronizer or FIFO for multi bit data.
1. You cannot simply synchronize data from clock domain A and B to clock domain C and then perform the combinational operation. This will result in classic problem of re-convergence. With synchronizers you cannot guarantee that data will be sampled in 2 clock cycles (assuming double flops for...
Synthesis tool should look at both paths as previously stated. There are few processor based companies that uses latch based designs with internal timing tools to gain from timing borrowing and stealing. However, you should always use negative level latch followed by positive level latch. In...
1. Can you use higher metal layers for routing to reduce interconnect delay?
2. Pipeline.
3. Upsize cells.
4. Add buffers to reduces interconnect delay.
5. Add low Vt cells which are faster but more power hungry.
As in you have lot of options. Just use all the basics of reducing delay.
As others mentioned question is not making much sense. It is be a good idea to read more about static timing analysis. Feel free to post relevant question if you encounter after that.
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