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Re: SOC Encounter CTS
could you try tracing this pin uPAD_MDQ_clk/OY in the preCTS def/nl.
i suspect, there are no flops connected to this pin. in that case, CTS would certainly fail to trace clock from this port.
The length of the tranisitor here signifies the Channel Length of the transistor. put this in standard CMOS equation to get a correct understanding
Ids = ..........................
I Suppose, mobility is another parameter that affects the working voltage.
see if you can refer Yousuf and Kang...
Re: Memory Synthesizes.
There is nothing called memory synthesis. but there is generally a Memory Compiler that generates the Frontend (library) and Backend (LEF) views of memories of given size. Artisan is one vendor providing such memory compilers.
Regards
Re: hazards
Hazards is referring to the wrong logic value being propogated along a gate due to difference (may call it skew) in the arrival of inputs to the Logic Gate
a 0 or 1 Hazard and a glitch are essentially same
Regards
Re: SRAM questions
Two port SRAM is smaller than dual port SRAM.
Two port SRAM is one port only for read and one port only for write.
Dual port SRAM provides two port for read or write.
Since it is Static Circuitry, the power consumption is largely dependent on the switching activity.
Check Out,
to eval the core area for a core limited design
a) check out the total # of signal pads required. Either it is obtained from front end or is determined from the knowledge of interfaces to the chip.
b) Total area occupied by the modules in the design is calculated. This area is...
Re: power planning
"CALCULATION OF CORE RING WIDTH"
This involves following steps
a) The width and height of the core area is obtained from estimation sheet
b) Current at the top/bottom and left/right is determined by the following equations
Itop = Ibottom = { Ict * [ Wc / (Wc +...
Re: SRAM comparison
I am not very clear about the difference between two port SRAM and a DUAL port SRAM.
also let me know about the convention 1rw / 1r_1w
Thanks
IR drop
IR Drop as said above is voltage drop from the PAD circuitry to the standard cells.
> The implication is the reference voltage VDD is different at different places in the chip causing on chip variations . Also, a ngative impact on timing due to reduced VDD => (Vdd - I*R)
> To keep...
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