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comparator hysteresis
Hello all,
I am currently using a simple latched comparator in a CT sigma delta ADC.
My question is with regards to deterministic and random hysteresis.
When I test the comparator and provide it with a very slowly rising ramp then, very close to the threshold, the...
Thanks for your response. I am not sure how one would go about this signal scaling.
As a simple example consider a desired 3bit output signal with 1V as reference. Now using an additional bit at the o/p of the sinc I could distinguish between 16 states. So the LSB is 1/16V. Assuming I want to...
Hello all;
Consider a sigma delta modulator with a sinc decimation filter.
The output will be a 7 bit digital signal. Power supply is 1.5V.
What I want to do is throw away roughly 100mV from the supply rails. So I want my effective output to be in the range of 0.1 to 1.4V. Hence I want the...
Hello all;
Consider a sigma delta modulator with a sinc decimation filter.
The output will be a 7 bit digital signal. Power supply is 1.5V.
What I want to do is throw away roughly 100mV from the supply rails. So I want my effective output to be in the range of 0.1 to 1.4V. Hence I want the...
Hello all,
I have a 3V i/p signal coming from an external RC pole (500Hz). The external resistance of the RC pole is not fixed but assumed to be in the 1k region. After the "almost" dc signal is passed on chip it needs to be divided down by 2 as power supply is 1.5V. It then feeds into a sigma...
sigma-delta single ended
Consider a simple first order single ended sigma delta modulator (RC integrator).
Being single ended one terminal of the RC integrator and comparator sits at the common mode level. Being a dc signal it causes spurs in the o/p spectrum. Is there a way of resolving this...
This has puzzled me a bit today.
Scenario 1)
Consider a fractional-N PLL. The VCO frequency goes into a chain of 2/3 dividers which are set by the sigma-delta modulator. The SDM works with a 16bit input word and produces a 3 bit output. Hence the divider divides by either N-3, N-2, N-1, N, N+1...
Thanks,
most of the signals I did verify using mixed mode simulations as each block has a verilogams view. However, this is more to check the interaction with the digital (verilog) block which controls the entire chip. ATB (analog test bus) lines and bias lines are not checked by the mixed...
Hello all,
this might be a trivial question but I was wondering how people go about checking whether there are no unintended connections in large designs.
Obviously, a "check and save" will reveal unconnected lines and also whether the signal lines have the same number of bits as the blocks...
Hello all,
So I was wondering how to choose the reference voltage for the DAC in the sigma delta ADC. Considering a 1.5V process the input sinusoid is centred around 750mV. With the quantizer levels of 1.5V and 0V what value do I need to feed back to the input. If I were to use 1.5 and 0V as...
I often read that " Phase noise performance is degraded by frequency multiplication at the rate of 20 log (N) whereas N being the multiplication factor".
Could someone please share their insight as to where this "20 log (N)" term comes about? Some literature references would be nice.
Thanks.
delta-sigma dead band
Hello,
I'm going for a job interview and a big part will be questions on delta-sigma A/D converters. I am wanting to prepare and would appreciate some feedback as to what might be asked.
BTW, it will be telephone interview at first.
cheers,
Ps I am familiar with the...
Re: JITTER QUESTION
Thanks for the response.
For a clock period T a jitter variation of T/4 would be sufficient, as T/4 delayed, plus T/4 advanced will already give an overlap.
JITTER QUESTION
I was modeling jitter as a random variation of the clock edges. So I randomly delay or advance a jitter free clock to obtain my non-ideal clock.
Now, since I have no experience with real life clocks I was wondering about the following:
Can it happen that one edge of a clock...
clock divider jitter
Thanks for the responses. My question regarding jitter effects has the following reason:
I was wondering whether multi-rate cascaded (MASH) sigma delta modulators might benefit from a slower clock in the first stage and higher clock in the second stage VS. a 2nd order...
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