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Recent content by sval

  1. S

    will a case statement work inside a for loop ( vhdl)

    for loop within case statement in vhdl try this process(clk,rst,ena) begin if (rst = '1') then for i in 0 to 2 loop case (i) is when 0 => when 1 => when 2 => end case; end loop; elsif (rising_edge(clk) and ena = '1') then for i...
  2. S

    convert std_logic_vector to integer in Quartus

    integer to std_logic_vector use ieee.numeric_std.all; ...<= to_integer(unsigned(....)); ...<= to_integer(signed(....));
  3. S

    How to interface with external memory in FPGA

    how to interface dram Try use SDRAM chip for external RAM. Look it download.micron.com/pdf/datasheets/dram/sdram/64MSDRAM.pdf Here u will find interface description for SDRAM.
  4. S

    Filter made with fdatool, how to apply it

    applying fda tool filter Export coefficients to workspace and use filter(...) function to apply ur IIR filter for given signal
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