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All Digital PLL
For 45, 65 and 90nm technology, the voltage headroom is decreased. and it's more and more difficult to design ADPLL with digital core device. Beside voltage headroom, the gate-leakage is also a big problem for loop filter design. Although thick-oxide device can be used to solve...
Power rails
For core limited case, if VDD and VSS rails are running above and below PAD, you may insert ESD devices beside PAD and in between VDD and VSS rails. That will make the I/O cell shorter but wider. You may save some area on your I/O ring. But the Latch-up will suffer if you don't add...
lvds specs 300ps at 1gbps
OK.
If you want to do the single-end termination on TX side. One of the method is to use the source follower on the driving side, and the other side you can use switching resistor. In order to control the impedance, you must design some kind of tracking ckt on the...
ieee1596
If the 100 ohm termination resistor on RX side match the LVDS channel impedance, then there is no reflection from RX side. But if not, then there will be 2nd reflection on TX side, and this 2nd reflection will come back to RX. So for some high-speed LVDS transmitter (>1Gbps), the TX...
Hsim is better.
This tool provide more capability to trade-off speed and accuracy on different blocks. But you must know your chip well in order to set the options properly.
ADit doen't provide this capability. You don't know exactly how the tool group/partition the circuirt. But for individual...
esd consideration
If you have sensitive I/O pad for internal analog circuit, you may need to cut the I/O ring into 2 sections. One is for digital I/O and PWR/GND pads, the other is for analog I/O and PWR/GND pads. Each section with their own vdd1, vdd2, vss1, vss2,.... The reason for this is to...
ring oscillator
Hi,
In terms of power and speed, less stage is better.But usually VCO gain of less-satge design is larger compared to more stage design. In terms of VCO phase noise, we don't want VCO gain too large. Another consideration is more-stage VCO is more sensitive to power-supply...
Hi,
Usually, the BJT drawing size provided by foundary is used for design due to modeling accuracy. As for BJT area ratio of the PTAT part, it depend on the offset voltage of the OPA used in bandgap. If you want to have small statistics deviation of your 1.25V output during production, you can...
In addition to all process corner, temperature and voltage variation, remember to consider bias current variation.
So the simulation of total combination should be;
5(process corner)x2(-20C,100C)x2(3V,3.6V)x2(bias variation)=40.
That will guarantee your yield !
how to check tools license in unix
Dear Sir,
i have the following setup issues, i need some one to help me out .
we plan to install license on sun workstation, the license is floating, but we plan to run the real simulation program on faster PC with RHEL AS3.0 OS installed. The actual...
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