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Recent content by surajrgupta

  1. S

    [SOLVED] Adding '1' to a std_logic_vector in VHDL

    Hi, Since it is observing change in CET, P should be replaced by temp carry: process(temp, CET) begin if CET = '1' then RCO <= temp(0) and temp(1) and temp(2) and temp(3); else RCO <= '0'; end if; end process carry;

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