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Recent content by surajkashyap

  1. S

    Doubt on IR drop in deep sub micron Tech nodes

    Doubt on Voltage scaling Hi, What is the limit on voltage scaling. Lets say voltage is scaled below 1V, since current in a MOS is proportional to square of voltage, wont the current reduce drastically thereby increasing the delay significantly and hence affecting the freq.
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    Doubt on IR drop in deep sub micron Tech nodes

    Hi Can someone explain how IR drop increases with scaling? Also, since the volatge is scaled, shouldnt the current reduce?
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    [SOLVED] [moved] Metal Layers in a chip.

    Can you explain a little more as to how its done?. It also increases relative pemittivity and gives rise to capacitance right
  4. S

    [SOLVED] [moved] Metal Layers in a chip.

    Hi All, In a chip is there an oxide filling between two metal layer? If yes, can you explain why is it done. Thanks, Suraj Kashyap
  5. S

    [Moved] Sub threshold leakage

    Hi all, Can someone explain how sub threshold leakage happens physically. Even when the voltage is zero, there is some amount of Ioff current, hows it possible? Thank you
  6. S

    Doubt on Interconnect

    Hi All, Suppose there is a long interconnect and we want to reduce the delay by adding buffers. Where should the buffers be added, at the mid point or towards the driver side or the destination side? Why? Thank you
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    setup time violation fixing

    I will try to answer you question, but someone please correct me if I am wrong. I have no experience in VLSI and I am still a student. Buffer is a back-to-back inverter with the first inverter being small and the second one being larger. So the logic preceding the buffer sees a lower gate...
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    Doubt in Verilog Synthesis

    Hi, Thank you so much for your reply. Can you elaborate a little more about the SDC file. Should a new SDC file be wriiten for every new design which you do? How to give timing information related to millions of path in todays high density asics
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    Doubt in Verilog Synthesis

    Hi All, The delay values given in Verilog statements cannot be synthesized by the tool, I have a doubt in this. The RTL designer would have given delay values to enhance timing and avoid timing failures and to bring about proper synchronization right. If this is not synthesizable, won't it lead...
  10. S

    Cache Design interview

    Thank you for the link. The interview is for backend VLSI circuit design position. Sorry I did not mention this in my previous post.
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    Cache Design interview

    Hi People, I have an interview for circuit design for a last level cache. Please suggest some good books and research papers on cache design to prepare for this. It would be very helpful if there are books with questions and answers in addition to concepts as well. Looking forward to hearing...
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