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Thanks for your answer
I have connected the DC bias source and ac current in series and I still have a plot that goes from Gohms to ohms over the frequency range.
However, for output impedance, I have a plot that seems correct w/ 150mohms
Hi everyone,
I need to characterize a buffer (OTA rail-to-rail with cascode stage and class AB output stage) but I have not understood how to correctly make the simulation to obtain input and output impedance.
So the amplifier is in feedback configuration and for input impedance I have...
Thanks for your answer, it makes thing clearer. I have defined the capacitive load (10pF).
However, because of the PMOS current mirror that biases the PMOS input pair, I can't increase current a lot because transistors rapidly goes towards linear region.
Anyway, I was asked to use this...
Hi everyone,
I'm trying to design a rail-to-rail amplifier with a folded-cascode stage (differential to single-ended stage). I have a 20µA bias. However, I have not succeeded in having a large bandwidth (it should be 40MHz) and I don't know how to do to obtain it. I can't increase current and...
Hi everyone,
I'm currently trying to use the gm/Id method in order to design an OTA.
Therefore, I want to plot the required graphs for this method that correspond to the technology I use.
Here is what I do :
For the Id/(W/L) graph versus gm/Id, I plot Id vs Vgs and get gm by taking the gm vs...
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