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Recent content by sunspot

  1. S

    How to wrap a black box with Synopsys Shadow LogicDft ?

    difficult dft question yes, you can type these commands in dc_shell-t or edit a file including these commands and then dc_shell-t -f commands.scr
  2. S

    DFT: Is there anyone who can tell me whether using serdes

    In order to reduce the package cost, I want use serdes data pins as scan data pin. So, I can take tx_n/tx_p and rx_n/rx_p as 10 scan_in and scan_out data. Is there a methodology to achive this goal? thx
  3. S

    How to wrap a black box with Synopsys Shadow LogicDft ?

    difficult dft question set_dft_configuration -shadow_wrapper set_wrapper_element [get_cell -hier your_ram] -type shadow set_port_configuration -cell your_ram -port D -write {WEN 0} set_port_configuration -cell your_ram -port Q -read {WEN 1} insert_dft
  4. S

    Who can tell me the difference in set_dft_signal?

    set_dft_signal -view It's kind of you to help me. But can't catch you, could you mind depicting in detail. What is the difference between test clock and test point clock? From the very begining of my involving in dft, I think the command create_test_clock as a declaration of test clock. When we...
  5. S

    Who can tell me the difference in set_dft_signal?

    set_dft_signal Who can tell me the difference between test_point_normal_data_clock and test_point_clock for the "set_dft_signal" command used in Autofix of DFT compiler? thanks
  6. S

    [question]: about synopsys dc constraint

    There is a path between D and CK, this is useful when check the Dff setup and hold. But I don't think there is a path from CK, though D, and reach some other endpoints
  7. S

    Max Transition Violation Fix

    max transition time violation the transition is decided by two factors: one is the input slew (transition), one is output load(including wire cap and fanout). If anyone of them is over the limit of Lookup Table in std cell library, inaccuracy is produced. So, fixing max_transition violation is...
  8. S

    How can i make one standard cell delay zero in my design

    If you run simulation, you can control the option of simulator. If you run STA, you can modify the standard library and SDF file
  9. S

    why after synthesis have assign?

    dc synthesis remove assigns If you don't fix assign, the astro may fail to pass drc. There are many articles to explain in solvnet, though they may not take effect as you expect in fact. You can write a script to modify the netlist.
  10. S

    what is the systhesis and timing models of a hard macro

    If the macro is a digital block, you can generate the timing model by gate level STA tool such as PrimeTime. If it is a mix-signal or analog, the transistor level STA tool pathmill may be a solution.
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