Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by sulabh

  1. S

    Gate oxide thickness

    Hi, you may find this thread useful - https://www.edaboard.com/threads/96192/ **broken link removed**
  2. S

    tanner complete user guid

    Here's a old thread that may help you: https://www.edaboard.com/threads/214273/#post906629
  3. S

    vlsi design certificate course syllabus

    Try this link: https://cdac.in/index.aspx?id=DVLSI_modules
  4. S

    Calibre DRC rule deck

    Hi, VARIABLE VIA2_W_2 0.5 ---> VIA2 is for M2-M3 via, W may be for width, and 0.5 can be dimension, but '2' may not necessarily represent layer2(I think its indication of rule number, though not sure). Cheers
  5. S

    Cadence layout tool refresher

    Following links may help you: **broken link removed** **broken link removed** **broken link removed**
  6. S

    about hspice output file

    Check your .lis file for errors and warning, also check your simulation deck for plotting options.
  7. S

    About MOS layout in 65nm?

    This will help in transistor matching in the device, as these are analog component and generally have sizes greater than the normal matching becomes critical.
  8. S

    [SOLVED] negative power numbers in .lib

    Hi, Can some one help me suggest some good ways to remove negative internal power numbers in .lib, apart for setting them as 0 in the tool command. Thanks.
  9. S

    Assura Binding file missing

    You can check Assura Devlopment guide for some examples in this link: https://web.mit.edu/fredchen/www/share/assuradev.pdf
  10. S

    LVS Error Report (Assura)

    you can compare the schematic netlist and the layout netlist for that, have you checked DRC before LVS
  11. S

    LVS Error Report (Assura)

    The layer of the pin seems to be correct(highest layer used for the net), the text must be in the text layer(tt, etc.). Do check the direction of the pin in the layout and if it is attached and not floating. Filter Statistics is the devices that the tool recognizes if filter option is set. Look...
  12. S

    6T Cell SRAM Design inTanner

    yes it can be done, this thread may help you with Tanner: https://www.edaboard.com/threads/214273/
  13. S

    Inquiry about good TCL refernce

    Is there any free book in pdf format available for TCL
  14. S

    Why we using Dummy transistior?

    You can find some more in earlier post: https://www.edaboard.com/threads/213795/
  15. S

    Looking for course for electronics hardware engineer

    Re: electronics hardware You can go for MS in VLSI from some good university or look for some training course available from CDAC or institute like them. Going for entry level job too is a good idea.
See more

Part and Inventory Search

Back
Top