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Hi, All,
Who can tell me the the following specification is difficult or not, especially on the phase noise? Why? Thanks!!!
VCO Frequency: 50MHz - 1050MHz.
Frequency Step: About 30kHz.
Phase Noise: 90dBc/Hz at 1kHz offset.
Power supply: 3.3V.
Process...
PLL Bandwidth
But you still can use the different bandwidth since you caontrol the PLL. Simply use the control singal for your different frequency output to control your loop bandwidth. It seems that you have adptive PLL loop.
pll design
As for low jitter, few suggestions for you
1)VCO itself shall have very small phase noise at out of the PLL loop bandwidth
2)The output of Charge Pump shall have very small ripple which require the good match on charge current and discharge current.
3)All bias for the circuit shall...
Substrate Resistance
Due to the distributed nature of the substrate, it is very difficult to caculate the real resistance since there are too many reference points. Cadence right now offer a tool called "VCA" can do the substate resistance extection.
sugar
charge pump design
Using the low Vth transistor and high gate voltage which beyond your power range will incrase the effeciency.
Or you must use the external device such as very low impedance switch.
The issue is the low impedance you got, the high effeciency you got
sugar
There is no limitation on the length except the process limitation and the model parameter accuracy limitation if you beyond certain value.
There is also no rule that length must be longer than width.
The length decision is solely because of the circuit requirement and process accuracy.
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