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Recent content by sudhamahesh70

  1. S

    what is the advantage of exclusive access in AXI?

    The main advantage of exclusive access is the master can have latest information of the register/memory (read transaction) and it will perform a write, like read-modify-write style....
  2. S

    Difference between Verilog and SystemVerilog

    There are lot of differences in verilog and SV. we can say, SV= verilog+ all features required for Verification +assertions. we have enhanced version of fork-join which is very usefull for parallel processes, oops, inter-process communications [semaphore and mailboxes] and also we can...
  3. S

    How to change the VCS random seed

    Re: VCS random seed use this command after compilation ./simv +ntb_random_seed=value Its working for me. --Mahesh

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