Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all
I am a graduate student specializing in VLSI design. I am trying to get acquainted with verification techniques and tools used in the industry. I am currently trying to understand the mathematical concepts of verification, like graphs, BDD, model checking, symbolic computation. But these...
Hi
I am looking for some good course material on VLSI Design Validation and Verification.. Can you please help me in finding the same.
Regards
Sudarshan
Hi all
I am currently designing SRAM with BIST which will run March tests to test the SRAM. I came across the IEEE 1149 standard for testing but was not able to find good documentation for memory test using IEEE 1149 standard. Here r a few quick question. Can you please help me in clarifying...
Hi Shailesh
Thank you for the response.. The explanation in brief is appreciated.
Well I am doing an academic project for my course work. I am planning to design and implement a SRAM with in-built test circuit (MBIST). Do you have any suggestions as to some references, papers, texts for MBIST...
Hi
Thank you Shakti and Sunil for the response. Well Shakti as you mention that tools like Mentor Graphics are required to perform DFT, I was wondering if we can implement DFT or BIST as a normal circuit design ie adding the extra circuit along with the actual circuit design. Let me know the...
Hi
This is Sudarshan. I am a Graduate student and I will be doing a project on Design for testability using BIST. I have a few queries regarding the same and It will be really great if I can receive your help. Here are few of my queries:
1. I am completely new to Design for Testability. I...
Hi all
Just a small reminder. Can anyone help me in finding information on Design for Test and Built in self test techniques. I have found 2 books:
Essentials of Electronic Testing - For Digital Memory and Mixed-Signal VLSI Circuits
VLSI Test Principles and Architectures Design for Testability...
I am looking for the methodologies.... I will be using Cadence to design the chip and would like to introduce some on-chip testing circuit. I am not aware of the testing methods and circuits.. It will be great if you can help me in finding some good material and some papers showing the...
Hi
I am a Graduate student in VLSI design. I am looking for some good material and some suggestions on a project on Design for Testing. Can you please help me in finding the same.
combinatorial loops
hi guys
thank you for the response..... yeah the accumulator required a clocking scheme... . so I used the same statement but triggered the statement only at the rising edge of the input..... something like, if 'a' is my input to the combinational logic
if(a=1 and...
xilinx combinatorial loop
Thank you for the response. Yeah the statement is valid only for sequential block, but in my design, I need to build a FSM in which there is a controller and ALU. The above statement is a part of the ALU which is a combinational process (ie no clk in the sensitivity...
combinatorial loop
Hi
I am facing a warning which says "The following signals form a combinatorial loop". I am trying to build a combinational circuit (this is a part of a complete FSM ie a different process and will not have a clock interface). Here I am using a statement like ...
HI
I am trying to write a 2-process model code for vhdl. i have defined a few signals to establish communication. Process 1 (Master) sets the signal which triggers the Process 2 (slave). Now I am trying to reset the same signal in the slave process, but this does not seem to be working. Can you...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
