Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thank you sir.
I will now proceed for the design of folded cascode diff amp. Sir what are the parameters to aim at and what is the gain that I can expect from the topology.?
Sir, as you mentioned if I keep the multiplier so that the power MOS is in saturation the Vg node is more than 1.4V if load is 0mA...And I found that, at 50mA load, for m=28 Vg is about 250mV and for m=37 Vg is about 500mV.. but at load current of 0mA it is increasing upto 1.35 making pow MOS to...
Here r d some results which i got..did the vg sweep for different values of multiplier got the results as in attachments...(W=50u L=180n)
for the power mos to be in saturation (1.62-Vg)-Vth<120mV which means Vg>0.985V (threshold was 0.515V)
also (1.62-Vg)>Vth implies Vg<1.105V... so...
I reduced the value of R1 and R2 to 100k and 200k so that they will draw 5uA of current if Vo is 1.5V ...instead of load current source of 50mA i have used 30 ohm resistor (1.5/50m)..but I am not able to get 1.5V at output as expected (so Vg thousands of volts) even though if I increase W of...
Sir I simulated the circuit u had suggested..I plotted Vg vs w for w varying from 1um to 20um but the Vg is in the range of 1.15V to 1.25V which means the power MOS is cutoff...and for case 2 I am getting some error in cadence.
these are the screen shots.
U can send me d link of d paper..bt presently i have to meet the specs which i have told abv, as a part of my project
- - - Updated - - -
thank u for explaining ur schematic...and yes i have been referring IIT video lectures (by nagendra krishnapura - d link u have mentioned) for past few months
Thank u SIDDHARTHA HAZRA i will follow ur circuit and try to design power MOSFET...i wil ask u further clarifications once i do it:-)
viperpaki007...can u please explain me the steps u followed to design this circuit from specs..
Thank u Siddhartha Hazra sir for ur kind specific reply...I will now look into power mosfet details..if possible pls explain the d difference betn usual mosfet and power mosfet and how its used in LDO..
and how much gain is expected from the error amplr, do i need two stage amplifier..?
js thank...
I am designing an LDO with following specs..
Vin : 1.8V +/- 10%
Vout : 1.5V +/- 3%
Vref : 1V +/- 1%
Iload : 0 to 50mA
Ext Cap : 100nF +/- 20%
PSR : >40dB upto 10MHz
please suggest me the way forward (where to begin the design wat parameters and architectures to look at etc.)..I have read abt...
Evn I am designing an LDO with following specs..
Vin : 1.8V +/- 10%
Vout : 1.5V +/- 3%
Vref : 1V +/- 1%
Iload : 0 to 50mA
Ext Cap : 100nF +/- 20%
PSR : >40dB upto 10MHz
Can anybody please explain me which method is better whether to proceed block by block like designing error amp then moving on...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
