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Recent content by styxies

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    [SOLVED] OTA Open Loop Gain and Phase Margin

    Hi All! I finally found the problem. Me being the inexperienced designer that I was, simulated the circuit together with the CMFB circuit inside. Which meant I had resistors connecting both my outputs and then was connected to a sense amp. When I simulated separate the OTA and the CMFB, the...
  2. S

    [SOLVED] OTA Open Loop Gain and Phase Margin

    Hi, thanks for the reply, do you have any suggestions how I can improve my test setup?
  3. S

    [SOLVED] OTA Open Loop Gain and Phase Margin

    Hi all, is it ok for the DC gain to be negative dB?
  4. S

    [SOLVED] OTA Open Loop Gain and Phase Margin

    Ok thanks. I will also try obtaining this waveform.
  5. S

    [SOLVED] OTA Open Loop Gain and Phase Margin

    Unfortunately, I need to have the open loop gain plot to have the gain bandwidth. This OTA is to be then used for a gm-c filter
  6. S

    [SOLVED] OTA Open Loop Gain and Phase Margin

    what do you mean? There's something wrong with my OTA?
  7. S

    [SOLVED] OTA Open Loop Gain and Phase Margin

    Even when I increase the resistance, it still results in negative dB gain.
  8. S

    [SOLVED] OTA Open Loop Gain and Phase Margin

    Hi all, I am trying to design an OTA, and I was checking it's phase margin and open loop gain, using the attached test bench, However, my obtained gain is negative. Around -40 dB. is my test bench wrong? How can I improve it? Thanks. Attached is the test bench and the resulting gain and...
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    MOS Saturation vs Output

    Hi, In some simulators the Operating Point of the MOS is given for time = 0, even for DC sweeps, the operating point is given for time =0. In this particular case I am using synopsys EDA tools, and my output is already correct. However, from the dc operating point report, some of my MOSFETs...
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    OTA design problem current not stabilizing

    Hi all, the problem was fixed by changing the testbench. Basically, I had a wrong testbench as my inputs were not totally differential. I needed to have a VCVS with negative 1 gain on my negative input terminal to balance it out.
  11. S

    OTA design problem current not stabilizing

    I actually tried with the both of them as the same, and the result was the same as well. I am told that this isn't actually a problem since when designing OTAs the goal is to keep the Gm relatively constant for a range of inputs, but I would need a textbook or journal citation to back this...
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    OTA design problem current not stabilizing

    I am sorry, here is the schematic with the test bench I am using. The test bench contains pad and esd parasitics since this is for tapeout.

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