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The maximum frequency your logic gates(ex. inverter) can handle depends on their driveability which is their ability to source (charge) or sink (discharge) the capacitive load. I*t=C*V where I is the source /sink current, t is the time to reach the voltage V from 0v, and C is the capacitive...
Try loading the CLK1 and CLK2 with the equivalent input capacitance of the charge pump and simulate it again to check the driveability of your inverter I5 and I6. Compare the waveform with and without load.
You can try to set the current across your transistor by referring to the formula Id=KW/2L *(vgs-vt)^2*(1+Lambda*vds).
You can vary vgs or W/L ratio to set the current and/or set a DC voltage drop across your Rload(Rdrain) which in turn will set your DC output level.
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