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Recent content by stephens_forest

  1. S

    solving setup time violation

    you can use two method: 1) strengthen your DC constraints. 2) re code your rtl and resynthesize. best regards
  2. S

    Problems with DFFs without RESET in simulation

    a good design practice is to use DFF with reset input, no reset input, DFT will be impossible. best regards
  3. S

    Question on digital Logic

    I thin you can follow following steps to construct a T FLIPFLOP by using Mux: 1) use Mux to construct two latch 2) use these two latch to construct a edge triggered DFF. 3) use this DFF and Mux to construct a TFF. best regards
  4. S

    TL 494 converter design

    tl494 schematic circuit I've found some topics on TL494, you can download them, I think they are useful. https://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=slva001d...
  5. S

    How to derive a state diagram based on the PROM data?

    eprom state machine PROM can only generate next logic and output logic for a state machine, PROM's address is current state input and other input, PROM's data is next logic and outputs. you can read PROM's content and convert them into truth table, perhaps use some logic reduction...
  6. S

    which one consumes less power?

    I think value 1 input will consume less power, because DFF's internal logic needn't change, but for input 0, the dff's internal logic will change, and internal node will be charged or discharged, consume greater power consumption. cmos power consumption formula: P = C*V*V*f (C...
  7. S

    how to analyze the timing of latch?

    I design digital system with DFFs, not use latch, In dff design, if a function is implemented by a pipelined structure, we can move some combinational logic between adjacent DFFs to balance timing and get higher operating frequency, this called timing borrowing. moving...
  8. S

    What are the general guidelines for inserting buffers ?

    Re: buffers buffer has two functions: 1) for fixing hold time, we add buffer before a dff's inputs to increase data delay. 2) for fixing transition time violation, we add buffers to increase drive ability. but in these case, buffer also increase delay by itself, but...

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