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Depending on the kit. In out company kit we have WPE enforced as a DRC rule to make sure you have suitable spacing, so as we have to meet it is not extracted part. it is easier to avoid it.
Vth variation with W/L is based on your DC operating point. You can plot that using a parametric sweep. As for reducing Vth, you need to try biasing your bulk, or use natives. Its a trade-off.
1) As Erikl mentioned you need levelshiters at the end of your Digital O/P to your analog Inputs.
2) to run a mixed mode sim, you can select a suitable connectLib, which will perform the necessary voltage domain transitions.
If you are taping this chip out i would prefer using levelshifters...
from you BW / load cap you can get the input gm required. decide gm/id. that will give you id required. the corresponding Id/(w/l) for given gm/id will get you length and width. the trick to get the right gm/id parameter depending on which device it is. (ie input/cascode/ load)
A good way to debug is to display message as to what code is doing and where it is.
I open an file and write message to it. you can use $strobe/ $display to see when you reach the generate statement and if it goes inside it.
You can share oxide diffusion to make them more compact. Sometimes bending poly can also help but this not recommended due to process constraints.
on second thoughts, optimizing the flip flop area may not necessarily give you a smaller area, routing spacing/density will start to affect the...
Reference voltages generally would be connected to points which dont draw current or very little. I suspect something is wrong in pipeline architecture/implementation.
if you need to pull 6mA out of your reference then you need regulators with that drive capability.
Phase margin and gain margin expressions are valid only when gain crosses unity and phase crosses -180. if these are not satisfied spectre will throw an error.
use an "if" statement to check if gain crossed unity and then calculate PM else set the output to some value you like.
i dont know...
Common centroid is a good practice. You should also keep in mind that splitting a 20x1 MOS into 4, 5x1MOS can have some effect on your simulation. it is better to double check.
You should also try to maintain symmetry in your connectivity.
You need to have another resistor between INP and the node connecting the current switches. That will help setup virtual ground (CM at inputs). In other words you need to have a DC bias condition.
Yes. that is how an op-amp works. Due to high open loop gain (theoretically infinite) with resistive feedback would force your inp and inn to be equal to the common mode value. the output common mode will be set based on the common mode feedback voltage. when you steer the current the output...
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