Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I need a simple block diagram with the single phase AC supply, all phases of the device, the common-mode choke, the switching elements, the ZCDs, and any ground or neutral connection.
Post #1 says the the ZCDs are "phase to phase".
Post #26 assumes that they are phase to neutral, and it got...
You haven't specified the data alignment, but a simple solution could be to use a 60-bit wide async FIFO.
Combine three 20-bit words to a 60-bit word on the write side, and write with 100 MHz.
Read with 100 MHz and split the data to two 30-bit words.
For a RAID storage, there must be a way to read the disks if the RAID system itself fails (and enough disks are OK).
My guess for the most long-lived disk interface from today is USB, that's why I suggested separate external USB disks (or internal disks together with a bunch of external...
I would probably use a few external USB disks, both spinning and SSDs.
With some years interval, you have to verify all of them, and replace any that fails.
B8 must be at address 0x7ff8 in the low byte EPROM, and 93 must be at address 0x7ff8 in the high-byte EPROM. When the 8086 goes to address 0xfff2 (and 0xfff3) the EPROMs will see address 0x7ff9.
Remember, A1 from the 8086 is connected to A0 of the EPROMs. A0 from the 8086 is not connected.
A0 is not connected to the EPROMs, so the addresses 0xfff0 and 0xfff1 will be 0x7ff8 locally to both of them. The 8086 uses A0 internally to select the low or high byte (only necessary for 8-bit transfers).
FvM's post #4 agrees with my experience from other processors. You don't connect the processor A0 to the memories at all. The processor A1 is connected to A0 on the memories, A2 to A1, etc.
The A0 processing is done internally in the processor, to use the low or high byte of the external data bus.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
