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Hi IamnotSam,
The properties in Q doesnot show any entry for the cell type. is there something else which can be done?
and these digital blocks are being done in virtuoso as they are small in size and will be used as a small part of Analog layout.
Hi all,
In Cadence Layout XL, the option place -> custom digital -> placement_planning, gives me the following error when I try to place the digital cells for auto place and route. Please help!!
Error in virtuoso CIW:
*WARNING* (VCP-3009): Could not run Placement Planning because the...
Preethi,
I think you are trying to add both the pins VSS and GND in the layout on the same substrate i.e the P+ substrate. As you know the substrate can have only one voltage i,e either VSS or GND. ( Though both voltages are zero, separation is needed to provide star connection to particular...
Preethi,
P diffusion guard ring means the ring with active layer, p+ diffusion layer, metal1 and contacts i.e basically its a P+ substrate pick up in the form of ring.
You can get diffusion rings by using create--> multipath part or create--> guard rings in the cadence virtuoso/icfb. Press F3...
Hi,
Here was an unanswered question from the previous closed thread:
I am running Calibre LVS. In schematic i have caps which are belongs to analoglib. So i am getting lvs errors. Please help me how to turn off or disable these caps.
Ans:
To filter the devices from analogLib library, use...
Hi all,
I have been doing analog layouts since three years and now I have been projected to the memory layout and the details are not known, project is for 6 months.
Somebody please let me know whether this is a good move or I should stick to analog layouts?
If you know, also please let me...
Hi,
There might be many weird reasons for this error. Try these solutions:
1. check if you have palced any symbol (view) in the layout by mistake. Search for symbol view and delete it
2. Make sure that all the schematic upto the lowest hierarchy is check and saved.
3. Make sure all the views...
I know that there are two kinds of metal fill viz, grounded dummy metal fill and floating dummy metal fill.
By using grounded dummy metal fill the de-coupling cap increases on the signals and thus induces a delay factor in near-by signals. I don't understand how floating dummy metal fill will...
Re: density rule in layout
Hi holla,
After the dummy fill is done, we don't connect them to any potential.They are left floating in the layout. Leaving the dummy fill floating will not affect the circuit working because we take care of the drc rules which will specify spacing between the metal...
Hi erikl,
I have one doubt. Referring to this patent "http://www.google.com/patents/US6091114"...
In the fourth last paragraph he says that when the n+ gated diode(n+ antenna diode)is connected to the NMOS gate and there is accumulation of positive ions, the n+ gated diode(antenna diode) gets...
Hi all,
Yeah I know that cdf is something using which we can change the most basic parameters of the components. But, one question always linger my mind. When I say refresh (Ctrl+r ) in the cadence/icfb window, it pops up a window where it asks "refresh CDF's? ". below this question there will...
Hi DharmaSlice,
After reading your post I now quite have a better idea on how the STI might affect. Can you please explain a little more on how the WPE and LOD are affected by the dummy filling of base layers?
And also which all base layers are checked for their density ? I have not come...
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