# Recent content by star_golden

1. ### [m]Is Output Voltage of the Synchronous Buck Converter independent of Load Resistance

Hi all, A lot of online sources (ex: Wikipedia) give the input-output voltage relation of the Buck Converter as Vout = D . Vin; where, D is the duty cycle of the driving PWM signal. But is the Output voltage of the Synchronous Buck Converter independent of the Load Resistance ? What happens...
2. ### [SOLVED] Verilog implementation for d/dt time derivative

Yes.. Thanks FvM, pancho_hideboo. I got it and fixed my problem. Thanks
3. ### What is the source voltage of High side MOSFET in Buck Converter ?

I am trying to model Buck Converter in Verilog. MOSFET model which I have designed has 3 inout ports - Source, Gate and Drain. During charging, High side MOSFET is ON, with the Inductor being charged. Drain terminal gets input voltage (12V) I have given PWM to the gate of MOSFET (When High side...
4. ### [SOLVED] Verilog implementation for d/dt time derivative

If f(t) changes linearly and time points are also linear (they are evenly spaced ) then, output df/dt will be a constant. Even though the input is changing linearly with time, output remains constant. Am I missing anything here ? How to solve this situation ?
5. ### [SOLVED] Verilog implementation for d/dt time derivative

Hi pacho_hideboo, What I understand from your post is : dI/dt = ((I at time 1 - I at time 0) + (I at time 2 - I at time 1)) / (time 1 - time0) Is this correct ?
6. ### [SOLVED] Verilog implementation for d/dt time derivative

Hello, I am trying to implement Capacitor and Inductor models in Verilog. These models have Voltage and Current equations which involve time derivative dI/dt and dV/dt. In Verilog AMS, we have a built-in function ddt(). But How do I implement these time derivative functions in Verilog ? Can...
7. ### Upper limit for sensitivity list elements in combinational block

a, b or c - Not clocks So, I did not get how it models sequential logic..?
8. ### Upper limit for sensitivity list elements in combinational block

Hi all, Is there is any upper limit in the sensitivity list for a combinatorial always block..? For eg : If the combinatorial always block code is like : always @ (posedge a or posedge b or negedge c...) begin end My question is : Is there like only 2 elements must be present inside the...
9. ### new to thw vlsi world....plz guide me

Yes.. I think that would be a better start. Pursuing M.S in USA really boost your career.