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Recent content by star_golden

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    [m]Is Output Voltage of the Synchronous Buck Converter independent of Load Resistance

    Hi all, A lot of online sources (ex: Wikipedia) give the input-output voltage relation of the Buck Converter as Vout = D . Vin; where, D is the duty cycle of the driving PWM signal. But is the Output voltage of the Synchronous Buck Converter independent of the Load Resistance ? What happens...
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    [SOLVED] Verilog implementation for d/dt time derivative

    Yes.. Thanks FvM, pancho_hideboo. I got it and fixed my problem. Thanks
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    What is the source voltage of High side MOSFET in Buck Converter ?

    I am trying to model Buck Converter in Verilog. MOSFET model which I have designed has 3 inout ports - Source, Gate and Drain. During charging, High side MOSFET is ON, with the Inductor being charged. Drain terminal gets input voltage (12V) I have given PWM to the gate of MOSFET (When High side...
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    [SOLVED] Verilog implementation for d/dt time derivative

    If f(t) changes linearly and time points are also linear (they are evenly spaced ) then, output df/dt will be a constant. Even though the input is changing linearly with time, output remains constant. Am I missing anything here ? How to solve this situation ?
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    [SOLVED] Verilog implementation for d/dt time derivative

    Hi pacho_hideboo, What I understand from your post is : dI/dt = ((I at time 1 - I at time 0) + (I at time 2 - I at time 1)) / (time 1 - time0) Is this correct ?
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    [SOLVED] Verilog implementation for d/dt time derivative

    Hello, I am trying to implement Capacitor and Inductor models in Verilog. These models have Voltage and Current equations which involve time derivative dI/dt and dV/dt. In Verilog AMS, we have a built-in function ddt(). But How do I implement these time derivative functions in Verilog ? Can...
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    Upper limit for sensitivity list elements in combinational block

    a, b or c - Not clocks So, I did not get how it models sequential logic..?
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    Upper limit for sensitivity list elements in combinational block

    Hi all, Is there is any upper limit in the sensitivity list for a combinatorial always block..? For eg : If the combinatorial always block code is like : always @ (posedge a or posedge b or negedge c...) begin end My question is : Is there like only 2 elements must be present inside the...
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    new to thw vlsi world....plz guide me

    Yes.. I think that would be a better start. Pursuing M.S in USA really boost your career.
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    Is this verilog code synthesizable?

    Not synthesizable. Probably you use $fwrite in testbench. So, why do you want to synthesize
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    Saving power in FPGA

    Instead of that or in addition to that, you may also want to try clock gating for power reduction. Turn on the clock only when it is necessary by asynchronously sensing the inputs
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    [SOLVED] HDMI to MIPI CSI2 solution

    You may also want to check with Bsquare Dragonboard
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    Running tcl script with arguments

    Hi, I open a text file which is there in the testbench. I open it like this : initial begin fd = $fopen ("../testbench/includes/data.txt", "r"); end Now I will have to open and process different text file each time I run the simulation. So, instead of changing the text file in the...
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    how to interface fpga to make a vending machine

    You can start with writing state machine for the design
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    How to give high impedence in verilog

    Hi, If you want to tristate then you can try "tri1" for pull up or "tri0" for pull down

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