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Recent content by stanford

  1. S

    min skew check

    Why do you want delay_clk > delay_data in Source-Synchronous path? Wouldn't this make the hold violation worse?
  2. S

    min skew check

    ah thanks, any other reasons?
  3. S

    min skew check

    Why do we have a check for min skew? What does this help avoid? Thanks!
  4. S

    source synchronous bus and hold violation

    When we send data and clk using source synchronous fashion, and if we assume that skew is ~0, the receiver could have setup and hold violations right? Why are we more concerned about hold violations with source synchronous bus? Isn't setup violation just as probable as hold violation?
  5. S

    Reset Value using a parameter

    I am using systemverilog, and it does not work. Syntax is not correct. Does anyone know how to fix it?
  6. S

    Reset Value using a parameter

    Let's say that I have a data[WIDTH-1:0]. I want to use a parameter in RTL to provide the reset value for this data. parameter RESET_VALUE = 5; logic [WIDTH-1:0] data; always_ff @(posedge clk) if (~reset) data <= WIDTH'd (RESET_VALUE); else .... How do I make this work syntax...
  7. S

    Using generate and for loop to index signal name

    Say I have inputs as follows: input in0; input in1; input in2; input in3; ... and what I want to do in generate for loop is something like this. b[0] = in0; b[1] = in1; b[2] = in2; ... and so on. The problem is I cant index the inputs using the variable 'i' in the generate for loop. How can...
  8. S

    default statement in case

    If i put this statement (state_nxt = state;) at the very top of the always_comb, the default statement in 'case' is not required for it to not synthesize into a latch. Is this correct? Would you still put the default statement for simulation purposes and why? always_comb begin state_nxt =...
  9. S

    Beginning and end of a time step

    I understand the theory, but I just wanted to make sure my understanding of the real life example makes sense. If someone has a good understanding of this topic, could you please confirm or correct it? thanks
  10. S

    Beginning and end of a time step

    Can you take a look at my steps above? I think you are saying the same thing.
  11. S

    Beginning and end of a time step

    input in; always_ff @(posedge clk) c <= a | b; always_ff @(posedge clk) in <= foo; always_comb begin a = in; b = a; end 1 2 3 clk __|--|__|--|__|--|__ foo ___|--------------------- in _______|------------- a _______|------------- b...
  12. S

    Beginning and end of a time step

    Let me give a more specific example to show what I'm confused about. input in; always_ff @(posedge clk) c <= a | b; always_comb begin a = in; b = a; end 1 2 3 clk __|--|__|--|__|--|__ in _______|------------- c ____________|------ In the wave...
  13. S

    Beginning and end of a time step

    I'm still confused. Let's say in the waveform, clk edge 0: a = 0, b = 0 clk edge 1: a = 1, b = 1 Now, at clk edge 1, the always_ff will be triggered and the RHS will be evaluated (a || b) = (1 || 1) = 1, or will it evaluate with the previous value (a || b) = (0 || 0) = 0? If the latter is...
  14. S

    Beginning and end of a time step

    Non-blocking assignment evaluates the RHS expression at the beginning of a time step and schedules the LHS update to take place at the end of the time step. Let's say we have always_ff @(posedge clk) c <= a | b; If we have a non-blocking assignment inside a always_ff block, does the...
  15. S

    Optimizing case statement with large input

    Maybe i dont understand how case statements get synthesized. How is this realized in hardware? case (input[1:0]) 0: ... 1: ... 2: ... 3: ... default: ... endcase How will these two look different in hardware? if (input[1:0] == 0) ... else if (input[1:0] == 1) ... else if...

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