Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by srikanth408

  1. S

    overcome limit on flight time and clock skew in source synchronous systems

    According to JEDEC standard, in source synchronous systems like ddr2 there is no limit on filght time between two ICs and no limit on Clock skew. How is it possible in ddr2 and not possible in ddr
  2. S

    no odt for address command control signals in ddr2

    Why does ODT only applies to data bus. Why don't we have on die termination for address command control signals in ddr2? Why do we use parallel termination(to Vtt) only for address command control signals in ddr. What are the disadvantages in using series termination. Why do we terminate...

Part and Inventory Search