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Recent content by srihari465

  1. S

    Genaration of lef file using synopsys tools.

    Hi All, Which tool is used in synopsys to Generate a lef file from GDSII. If possible please attach relevant document. Thanks, Srihari
  2. S

    Half cells regarding to matched transistors

    Hi, Can any one please explain me, how to do half cells regarding to matched one. If possible Please attach documents. Thanks, SRIHARI Ω
  3. S

    decreasing bottom plate parasitics in MOM capacitors

    By placing Nwell or a D-Nwell the capacitance can't be reduced, i think the only way is to use a higher level metal as the bottom plate....
  4. S

    Cut poly in TSMC 28nm

    Yup, Its mentioned as 'Double PO patterning' in DRD and 'Poly double cut' in Layer Usage Description file. Read the Design Rule Document it contains every info you wanted....
  5. S

    positive and negative plates of MIM capacitor

    we can identify the top & bottom plate by checking the layers. For eg: if a mim is comprising of Poly to M3 metal layers, Poly will be the bottom & M3 will be the top. For connection purpose you need to follow the MIM layout rules in the Design rule document.:grin:
  6. S

    Cut poly in TSMC 28nm

    Check page 21 of the Design rule document.
  7. S

    Cut poly in TSMC 28nm

    Yup, it is mentioned as 'Double PO patterning' ...........
  8. S

    Cut poly in TSMC 28nm

    I' m not sure ..but in TSMC 28nm PDK it's mentioned like CPO is for 'Double PO patterning'
  9. S

    Cut poly in TSMC 28nm

    Yes , its correct what Sergio told, TSMC 28nm is not using Double Pattern Lithography.But Cut masks are used only in DPL. Can you tell what exactly is the lithographic process used in TSMC 28nm. Regards Sreehariii.......
  10. S

    Cut poly in TSMC 28nm

    Hi All, Currently I am working on TSMC 28nm process, can anyone tell what's the use of a Cut Poly layer??? Regards Sreeharii
  11. S

    2nd Poly Space Effect

    I am expecting answers from such guys only....:lol:
  12. S

    2nd Poly Space Effect

    Hi all, What is meant by 2nd Poly Space Effect? Plz explain in detail, if possible provide some ref............... Thanks & Regards Srihari :-(:-(
  13. S

    thin & thick gate oxide

    Hi all thanx for all your responses... But I read like thin gate should be used in preference to thick gate for better matching in the book Art of Analog layout by Alan Hasting Page No.442 4rt para. If someone knows the answer for this please reply. Thanks & Regards Srihariii
  14. S

    cadence skill command doubt

    Hii all Please tell the usage of "schiCreateSymbolShape" skill command, Is it same as "schHICreateSymbolShape" else whats the difference. Thanks & Regards Srihariii
  15. S

    thin & thick gate oxide

    Hi all, Which MOSFET match better, one with a thin gate or a thickgate oxide?? Why?? Please explain in detail. Thanks & Regards Srihariii
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