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Recent content by sreevenkjan

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    Want verilog code for generating Trigger signal for 500ns

    Try writing a testbench and check what the counter does, as dpaul mentioned you do not need 2 counters. If you need the trigger at 500ns then I would suggest you to look at the counter value condition while setting the timescale in testbench.
  2. S

    Creating real-time data log of FPGA sensor readings

    Do you have a block diagram? Why do you need FPGA? (just for display). I feel you are complicating the design. You can avoid the FPGA if you just need it as 7 segment display because the design can get complicated using the board. If you have a time constraint then I suggest developing in on PC...
  3. S

    Implemtation Mapper Error

    which 2 lines are you talking about? Memory is the top module right??
  4. S

    [SOLVED] this code for interfacing ADC 122S101 is not working

    Can you tell the clk and sclk value? In the pic share above in your first post, is the waveform of your clk and sclk signal the same? There is missing information of your clk in the timing diagram, can you repost the timing diagram with clk signal in it?
  5. S

    Interfacing Python C1300 Camera Module with Zedboard

    What do you mean by how to provide the signals? The interfaces I2C/SPI are meant to write/read in to the Python CMOS sensor registers. So you need to look into the registers setting of the CMOS sensor to program the sensor. Through FPGA you can do it.
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    [moved] Simulator and synthesis tool required

    Did you try it with a student email id? Which software are you trying to use? If you are using 3rd party vendors then u need to buy license and they are not free. But as Barry mentioned the common Xilinx and Altera(Intel) should be free.
  7. S

    [SOLVED] this code for interfacing ADC 122S101 is not working

    I suggest you do not use nxt_state and assign the state signal to idle or read parameters. If you are planning to then u need to define it properly so that it shifts from state to nxt_state or you can simply write state instead of nxt_state. 1. Instead of using nxt_state use state = idle/read...
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    [SOLVED] Verilog error, Please help

    Re: Verilog error , Pls help if you have a look at my post #4, I suggested to check the settings, in this case I would suggest you to choose appropriate FPGA and then compile the project. you cannot have 1 device and compile the project meant to be for another device. It does not work like that.
  9. S

    Want to convert 32 bit data into 4 group of 8 bit data for UART

    Re: [Moved] how to synchronize 32bit (live) data with UART on spartan 3E. how is the data coming? Is it axi protocol compatible? If yes then I suggest you go through the below link. You can find examples. Show us the code which tells about the function of filter...
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    AXI4 to AXI Stream conversion for Ultrascale PCIe EP support

    well I want to build a hardware with PCIe Stream IP (Ultrascale PCIe IP), I have a AXI MM source. So I send my AXI MM signals to AXI Stream FIFO and then to PCIe Stream IP. on the other side I have AXI Datamover which receives signals from PCIe IP and then does the AXI Stream to AXI MM...
  11. S

    Work window is Altera Quartus II software

    check what u have defined cx_1 as, and like tricky mentioned, post the code so that we can help but I am sure you can find a solution for this from google as well.
  12. S

    AXI4 to AXI Stream conversion for Ultrascale PCIe EP support

    I decided to use AXI Stream FIFO and AXI Datamover. AXI Stream FIFO would be from MM Master to streaming slave and from Streaming slave to MM slave I would use AXI Datamover. Yes you are right the AXI Datamover uses streaming interface for control i.e for sending address commands. The Ultrascale...
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    [SOLVED] Verilog error, Please help

    Re: Verilog error , Pls help how is it possible that you could pull it off with Spartan-6? did you check the settings? as ads-ee suggested you can declare the variables earlier and also move the "assign" blocks down
  14. S

    Verilog testbench help!! (bit urgent)

    Have a look at the code in the link below and use it in your testbench, do the necessary changes in your testbench. Why dont you use Google? https://stackoverflow.com/questions/16630319/how-to-read-a-text-file-line-by-line-in-verilog

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