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Recent content by sreenu236

  1. S

    help reguired in verilog.....

    ok thanq very much.....
  2. S

    help reguired in verilog.....

    i am writing different modules in same verilog file.so i want use same parameter in all modules. how to declare "parameter" command globally ex:
  3. S

    advantages of decimation filter....

    any one can help what are the advantages of decimation filter, and application of decimation filters.please suggest me good and material for this topic. thanx in advance.
  4. S

    verification of a design...

    can any body please explain what is the verification of a design in vlsi. In vlsi flow at what stage verification is happening.please suggest some books and material for this topic. thanx in advance.
  5. S

    FIR/IIR Filter design Implementation

    fir iir filters thanx for posting this......
  6. S

    How to draw stick diagrams??

    Re: stick diagrams hi... check this link.. **broken link removed**
  7. S

    good thesis topic...........ASIC design

    hi... all this is srinivas.. pursuing my final MTech. my area of intrests is ASIC design. please suggest me good thesis topics.. thanx in advance .
  8. S

    difference between clock buffer and ordinary buffer

    what is the difference between clock buffer and ordinary buffer.
  9. S

    difference between ASIC verification , validation

    asic validation what is the difference between ASIC verification , ASIC validation and ASIC testing.
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